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Presenter: Poul Engelsted Holm

Faculty Sponsor: Russell Tessier

School: UMass Amherst

Research Area: Engineering

Session: Poster Session 6, 4:15 PM - 5:00 PM, 163, C8

ABSTRACT

Timing is a critical aspect in many digital systems, especially in synchronous digital systems, often dictating how data is processed, transmitted, and stored. Systems such as CPUs, GPUs, ASICs, and FPGAs (Field Programmable Gate Arrays) all perform numerous calculations that depend on clock synchronization. However, even after a circuit has been synchronized, clock skew can still occur through jitter taking place within the system. This paper focuses on period jitter, which is the maximum deviation of clock periods, and the effects it has on clocked circuits at different clock frequencies. Experiments conducted in this paper also test to see if the jitter on the FPGA board can be reduced by setting physical constraints and to understand how heated temperature conditions affect the jitter within a circuit on the FPGA. All testing was conducted using AMD’s free Vivado software and the Xilinx ZYBO Z7 FPGA board, selected for their availability and compatibility. The input signals used ranged from 10 Hz to 1 KHz, and the circuit's output counter would be compared to the built-in system clock set to 100 MHz. Additionally, each input signal would also be tested under heated conditions, up to 125 degrees Fahrenheit, to understand jitter effects. Results gathered from these tests show that as the clock frequency increases, jitter has less strain on the circuit as the counter is closer to the expected result, however, heated environments can drive the circuit up to, or past the clock’s tolerance.